The present invention relates to an electrostatic discharge (ESD) protection circuit for a sub-micrometer silicon integrated circuit (IC), and more particularly, to an adjustable trigger voltage circuit for ESD protection.
With the MOS technology progressing into the deep sub-micrometer design rule regime, thinner gate oxides become necessary. This results in lower oxide breakdown voltages which, in turn, require ESD protection devices or circuits which trigger at much lower and lower voltages. The requirement for ESD protection to trigger at lower voltages is not easily solved. Heretofore, such devices as grounded-gate NMOS transistors and Zener diodes have been used for ESD protection. However, such devices cannot achieve semiconductor junction breakdown voltages (used in the trigger mechanisms for ESD protection structures) below the Fowler-Nordheim tunneling threshold of the thin oxides used in deep sub-micron devices. The IC devices which use deep sub-micrometer design rules have oxide breakdown voltages below 5 volts, and supply voltages down to about 1 to 2 volts. Therefore, it is desirable to have an ESD protection circuit with triggering voltages less than 5-6 volts while maintaining low leakage currents. Also, it is desirable that such ESD protection circuits use universally compatible silicon IC technology.
An ESD protection circuit having a reference source means, an adjustable offset means. and an amplifier having an input and an output. The reference source means and the adjustable offset means are connected to the input of the amplifier. A positive ESD clamp is connected to the output of the amplifier.